This invention pertains to microlithography (projection-transfer of a pattern, defined on a reticle or mask, to a substrate that is xe2x80x9csensitivexe2x80x9d to the energy beam, used for the pattern transfer, in an image-forming way). Microlithography is a key technology used in the manufacture of semiconductor integrated circuits and displays. More specifically, the invention pertains to microlithography performed using a charged particle beam such as an electron beam, with correction of certain proximity effects.
Most conventional microlithography utilizes light (especially ultraviolet light) as the energy beam for performing pattern transfer. Light-based microlithography is termed xe2x80x9copticalxe2x80x9d microlithography. However, as the complexity and miniaturization of electronic devices (e.g., microprocessors, memories, and displays) has continued to increase, the resolution limitations (arising from, e.g., diffraction phenomena) of optical microlithography is more and more problematic. Hence, considerable development effort is being expended to develop a practical microlithography technology that can achieve better resolution of pattern elements, especially at line-widths of 0.1 xcexcm (100 nm) or less. To such end, utilization of other types of energy beams is being investigated for microlithography, including various charged particle beams such as an electron beam subjected to an acceleration voltage of several tens of KV to about 100 KV.
A charged-particle-beam (CPB) microlithography apparatus employs a charged particle beam (e.g., electron beam or ion beam) as an energy beam by which a pattern defined on a reticle is projection transferred to a suitable substrate (xe2x80x9cwaferxe2x80x9d). Certain aspects of a conventional CPB microlithography apparatus 80 are depicted schematically in FIG. 1. The FIG. 1 apparatus 80 employs a conventional reticle 90 that defines the pattern, and comprises an illumination unit 81, a reticle stage 82, a projection unit 83, a wafer stage 84, and a control unit 85.
The illumination unit 81 produces and directs a charged particle beam (e.g., electron beam) from a source toward the reticle stage 82. The reticle 90 is mounted to the reticle stage 82 such that the charged particle beam from the illumination unit 81 illuminates the reticle 90. The beam between the source and the reticle 90 is termed the xe2x80x9cillumination beamxe2x80x9d IB.
The reticle 90 xe2x80x9cpatternsxe2x80x9d the charged particle beam in an image-forming way. Certain aspects of a conventional CPB reticle 90 are depicted schematically in FIG. 2, including an alignment pattern 91 and multiple nearby circuit elements 92 of a xe2x80x9cchipxe2x80x9d pattern. The illumination beam IB from the illumination unit 81 passing through the depicted region of the reticle 90 illuminates the alignment pattern 91 and the circuit elements 92. As the illumination beam IB passes through the depicted portion of the reticle 90, the beam is patterned according to the illuminated alignment pattern 91 and circuit elements 92. In this context, xe2x80x9cpatternedxe2x80x9d means that the beam propagating downstream of the reticle 90 acquires an ability to form an image of the illuminated portion of the reticle.
The patterned beam PB propagates from the reticle 90 to the projection unit 83. The projection unit 83 is configured to deflect the patterned beam PB laterally as the beam propagates toward the wafer stage 84. The magnitude and direction of deflection is according to a command C input to the projection unit 83 from the control unit 85. The command C is an electrical signal encoding the desired position on the wafer 86 to which the patterned beam PB is to be deflected so as to expose the wafer 86.
The wafer 86 can be any suitable substrate but is usually a semiconductor wafer (e.g., silicon wafer), and hence the general term xe2x80x9cwaferxe2x80x9d is used herein. The upstream-facing surface of the wafer 86 is coated with a xe2x80x9cresistxe2x80x9d that is sensitive to exposure by the patterned beam. Thus, as the patterned beam PB impinges on the resist, the resist is imprinted with a latent image of the illuminated portion of the reticle 90. For exposure, the wafer 86 is mounted to the wafer stage 84. Typically, the wafer 86 is sufficiently large to accommodate multiple chips being formed on it, wherein each xe2x80x9cchipxe2x80x9d is destined to become a separate semiconductor device.
The control unit 85 is a device (e.g., microprocessor or analogous controller circuit) configured to control operation of the illumination unit 81 and the projection unit 83. For example, the control unit 85 controls the turning ON and OFF of emission of the charged particle beam by the illumination unit 81.
Thus, an image of the circuit elements 92 and an image of the alignment pattern 91 are xe2x80x9ctransferredxe2x80x9d to the sensitized surface of the wafer 86. The image of the alignment pattern 91 is termed an xe2x80x9calignment mark.xe2x80x9d
In addition to control of minimum line-width, other crucial aspects of microlithography as applied to the manufacture of semiconductor devices are throughput and registration accuracy between the various layers of each chip that must interconnect accurately with each other in the chip. xe2x80x9cThroughputxe2x80x9d is the number of wafers that can be processed microlithographically per unit time.
In conventional mass-production of semiconductor devices in which optical microlithography is used, alignment marks are employed that are detected by an optical-based alignment-detection method such as LSA or FIA. Certain alignment marks are situated in spaces between chips as formed on the wafer, and are used for various purposes including ensuring accurate exposure position of each chip and accurate registration of the various layers in each chip with each other. Such alignment marks are also important in CPB microlithography.
CPB microlithography is subject to a phenomenon termed xe2x80x9cproximity effectsxe2x80x9d as known in the art. With respect to elements as projected onto the wafer, proximity effects are manifest as, e.g., mis-shaped elements and reduced resolution of pattern elements situated proximally to each other. Proximity effects are caused largely by scattering of incident electrons within the resist and/or other materials on the wafer. Scattered electrons can have undesirable effects such as at least partial xe2x80x9cexposurexe2x80x9d of the resist in regions traversed by the scattered electrons, thereby degrading pattern-transfer accuracy and resolution. Therefore, correction of proximity effects is an important aspect of achieving practical CPB microlithography.
In CPB microlithography, the degree and extent of electron scattering from a point of incidence on the wafer is a function of the beam-acceleration voltage. I.e., as the acceleration voltage is increased, the depth and horizontal distance in the resist traversed by scattered electrons correspondingly increases. This phenomenon is depicted in FIGS. 3(a)-(b) in which the respective electron-scatter trace diagrams were created by a Monte Carlo simulator, and the hypothetical resist thickness was 0.5 xcexcm on a silicon substrate. FIG. 3(a) is an electronscatter trace at a beam-acceleration voltage of 30 KV, and FIG. 3(b) is an electron-scatter trace at a beam-acceleration voltage of 100 KV. The abscissa (horizontal axis) is distance of lateral propagation from the point of incidence, and the ordinate (vertical axis) is depth from the point of incidence on the resist surface. As shown in FIG. 3(a), the lateral (horizontal) extent of electron scatter from the point of incidence is approximately 7 xcexcm with an electron beam subjected to an acceleration voltage of 30 KV. The lateral scatter is 15 xcexcm to 20 xcexcm at an acceleration voltage of 50 KV (not shown), 35 xcexcm to 40 xcexcm at an acceleration voltage of 75 KV (not shown), and in excess of 65 xcexcm at an acceleration voltage of 100 KV (FIG. 3(b)).
Hence, in CPB microlithography, whenever a wafer is exposed using an electron beam having an acceleration voltage on the order of several tens of KV to 100 KV or more, proximity effects can be substantial. Despite application of conventional methods for controlling proximity effects in CPB microlithography, especially such methods used to control proximity effects of actual pattern elements, proximity effects remain troublesome.
Conventionally, some correction of proximity effects of elements within chip boundaries usually is performed in CPB microlithography. Among various conventional approaches for correcting proximity effects are control and variation of the dose of the patterned beam on the wafer, use of multi-layer resists, pattern-biasing (reshaping and/or resizing of pattern elements), and xe2x80x9cghosting.xe2x80x9d An example background reference describing various conventional methods for correcting proximity effects is Owen and Rissman, xe2x80x9cProximity Effect Correction for Electron Beam Lithography by Equalization of Background Dose,xe2x80x9d J. Appl. Phys. 54(6):3573-3581, June 1983.
Of the conventional methods for correcting proximity effects, the technique of controlling and varying the dose of the patterned beam on the wafer requires that the scattering of electrons in the thickness dimension of the wafer be determined in advance in order to determine the dose variation needed for correction. This technique also is difficult to apply to CPB microlithography apparatus that scan the reticle and substrate in a raster manner during exposure. In the technique of using multi-layer resists, applying and developing the resists are complex. The technique of pattern biasing is problematic because it involves extremely intricate adjustments of pattern-element dimensions and highly complex calculations to determine which adjustments to make and where to apply them.
The conventional technique of correcting proximity effects by xe2x80x9cghostingxe2x80x9d eliminates certain of the problems, listed above, encountered with other conventional methods of correcting proximity effects. In the ghosting technique, a defocused energy beam that has passed through a xe2x80x9ccorrectivexe2x80x9d reticle is irradiated onto the resist either before or after exposing the resist with an actual pattern defined by a conventional reticle. The ghosting exposure, in combination with the actual pattern exposure, results in a more even exposure overall from scattered electrons (i.e., an overall more uniform energy absorption by the resist).
In the most fundamental ghosting method, the energy beam is defocused by the horizontal distance into which the incident electrons will scatter in the resist. Within the boundary of a chip, the ghosting beam is irradiated onto regions of the wafer outside regions in which actual pattern elements have been or will be exposed. The ghosting dose normally is less than the dose used for exposing the pattern elements.
Conventionally, ghost exposures are performed at low beam-acceleration voltages that produce very little scattering of electrons in the resist. However, with current demand for higher-energy pattern-exposure beams, a need for correspondingly higher-energy ghost-exposure beams has become apparent.
A ghost exposure also causes scattering of electrons in the resist as a function of beam-acceleration voltage. Also, as the beam-acceleration voltage for pattern exposure is increased, the regions requiring a corrective ghost dose so as to achieve an overall more uniform energy absorption by the resist correspondingly expand.
At pattern-exposure beam energies sufficient to produce lateral scattering of several tens of xcexcm, it has been found that proximity-effect correction at or near the boundaries of the chip fields is not achieved adequately. I.e., conventional methods do not provide a corrective irradiation field capable of making uniform the energy accumulation in the resist in regions just outside the boundary of the chip field. As pattern-exposure beam energies continue to increase, proximity-effect correction near the boundary of the chip field becomes increasingly difficult to achieve by conventional methods, producing unacceptable irregularities in the energy accumulation in the resist within chip boundaries. More specifically, as chip patterns are exposed at increasingly higher beam-acceleration voltages using conventional ghosting methods, with respect to pattern elements extending to a chip-field boundary, the area of the pattern at the chip-field boundary becomes unexpectedly thick or thin. This makes it difficult to expose an intricate pattern with acceptable accuracy according to the design specifications.
This point is explained in more detail with reference to FIGS. 4(a)-4(c) and 5(a)-5(b). FIG. 4(a) depicts a chip field 142 on a wafer 141 (i.e., on a substrate to which a coating of resist has been applied). FIG. 4(b) is an enlargement of the region of FIG. 4(a) in the vicinity of a corner point xe2x80x9cAxe2x80x9d, according to design specifications. FIG. 4(c) is an enlargement of the region of FIG. 4(a) in the vicinity of the point xe2x80x9cAxe2x80x9d after wafer processing using conventional methods. FIG. 5(a) shows exemplary elements of the pattern, as defined on a conventional xe2x80x9cpatterning reticlexe2x80x9d 145, in the vicinity of a point xe2x80x9cAxe2x80x2xe2x80x9d, and FIG. 5(b) shows a conventional xe2x80x9cghosting reticlexe2x80x9d 146 in the vicinity of the point xe2x80x9cAxe2x80x2xe2x80x9d. (Point Axe2x80x2 in FIGS. 5(a) and 5(b) corresponds with the point A in FIGS. 4(a)-4(c).) For purposes of discussion, the wafer 141 is understood to be coated with a negative resist.
Normally, exposure of a chip field 142 is performed by the patterned beam within the boundaries 140 of the chip field 142. As shown in FIG. 4(a), the chip fields 142 are arrayed in two dimensions on the wafer 141 with specified gaps between them. In FIG. 4(b), the regions denoted by the numeral 143 are elements of the chip pattern actually exposed by the patterned beam. The regions 143 conventionally are not exposed by the corrective beam. The regions denoted by the numeral 144 are regions of the chip pattern exposed by the corrective beam. The regions 144 conventionally are not exposed by the patterned beam.
To achieve the type of exposure on the wafer as shown in FIGS. 4(b)-4(c), a xe2x80x9cpatterning reticlexe2x80x9d 145 (such as shown in FIG. 5(a)) is used for exposure using the patterned beam, and a xe2x80x9ccorrectivexe2x80x9d (e.g., ghosting) reticle 146 (such as shown in FIG. 5(b)) is used for exposure using the corrective beam.
As is usual with CPB microlithography, the chip field 142 is not exposed all at the same instant. Rather, the patterning reticle 145 is divided (segmented) into multiple subfields (not shown) arranged in a two-dimensional array on the patterning reticle 145. The corrective reticle 146 is divided similarly. Also, even though the image produced by passage of the patterned beam PB through the projection unit 83 (FIG. 1) is reversed, FIGS. 5(a)-5(b) do not indicate such reversal in the interest of simplifying this discussion.
FIG. 5(a) shows a portion of a subfield 147 on the patterning reticle 145 that corresponds to the subfield in the upper-left corner of the chip field 142 (FIG. 4(b)) and including point A. FIG. 5(b) shows a portion of a subfield 148 on the corrective reticle 146 that corresponds with the subfield in the upper-left corner of the chip field 142 (FIG. 4(b)) and including point A.
Even though not shown, the elements of the respective patterns defined by the reticles 145 and 146 are defined in part by scattering bodies exhibiting a large beam-scattering angle. I.e., the reticles 145, 146 are xe2x80x9cscattering-membranexe2x80x9d reticles as known in the art. In FIG. 5(a), regions denoted by the numeral 149 are regions in which no scattering body is present; scattering bodies are present in the intervening regions. Hence, in FIG. 4(b), the regions denoted by the numeral 143 are exposed by the patterned beam passing through the regions 149. Similarly, in FIG. 5(b), regions denoted by the numeral 150 are regions in which no scattering body is present; scattering bodies are present in the intervening regions. Hence, in FIG. 4(b), the regions denoted by the number 144 are exposed by the beam passing through the regions 150.
Alternatively to scattering-membrane reticles, each of the reticles 145, 146 can be a respective stencil reticle.
In a conventional ghosting method, the regions 144 in FIG. 4(b) are exposed using a xe2x80x9ccorrectivexe2x80x9d beam (set to provide an irradiation dose that is smaller than the dose provided by the patterning beam) passing through the reticle 146. Exposure of the regions 144 is made either before or after exposure of the regions 143 in FIG. 4(b) using the patterning beam passing through the reticle 145. If the beam-acceleration voltage used for exposing the pattern is at a level where lateral scattering of electrons in the resist is several tens of xcexcm, then not providing a corrective irradiation field to even out the energy accumulation (in the resist) in zones immediately outside the boundaries of the chip field 42 makes it impossible to achieve an adequate proximity-effect correction in the vicinity just inside the boundaries of the chip field. As a result, when the wafer 141 is developed after exposure, pattern elements 151 that (according to FIG. 4(b)) should extend to the boundary of the chip field 142 fail to do so, as shown in FIG. 4(c).
Another aspect of proximity-effect control that conventionally is not addressed is the incidence of proximity effects between a peripheral alignment mark on the wafer (outside the edge of the chip field) and nearby pattern elements within the boundary of a neighboring chip. By way of example, FIG. 6(a) depicts a situation in which an alignment mark 22 (consisting of multiple elements 24) is situated outside and adjacent a chip boundary 23. During actual exposure and development, due to the proximity of the alignment mark 22 to the chip boundary 23, the line-width of the elements 24 of the alignment mark 22 can be altered undesirably. Such a change to the alignment mark 22 degrades the line-width accuracy of the alignment mark and causes problems, depending on the circumstances, such as elements 24 of the alignment mark touching each other, etc. FIG. 6(b) shows adjacent elements 24 of an alignment mark 22, as exposed onto the wafer, touching each other, as caused by the proximity of the mark 22 to the adjacent element 21 of the nearby chip. If such a mark, as projected, is used to ascertain registration of a subsequently applied layer to the chips on the wafer, registration accuracy is decreased, which lowers the yield of chips from the wafer that are within specifications. This kind of problem can arise regardless of steps taken to reduce proximity effects on pattern elements within the chip boundaries.
Also, just as elements of a chip pattern inside a chip boundary can exhibit an undesirable proximity effect on nearby alignment marks situated outside the chip boundaries, the presence of alignment marks outside a chip boundary can exhibit an undesirable proximity effect on nearby elements of the chip pattern inside the chip boundary.
Conventional methods for proximity-effect correction do not correct proximity effects imparted to images of circuit elements, as projected onto the wafer, by an image of an adjacent alignment pattern. As a result, the profiles of pattern elements as projected onto the wafer frequently are distorted by proximity effects caused by the image of the adjacent alignment pattern.
In view of the shortcomings of the prior art summarized above, an object of the invention is to provide charged-particle-beam (CPB) microlithography (projection-exposure) apparatus and reticles that do not exhibit distortion of the images of circuit elements that are situated adjacent an alignment mark.
To such end, and according to a first aspect of the invention, microlithographic reticles are provided. A first example embodiment of a reticle comprises a pattern field and at least one alignment subfield. The pattern field comprises multiple circuit subfields in which are disposed respective circuit elements of a circuit pattern defined by the reticle. The alignment subfield includes a respective alignment pattern. The alignment subfield is disposed outside the pattern field but adjacent a respective circuit subfield. The alignment subfield can be disposed at a position at which the respective alignment pattern would be exposed onto a scribe line of the pattern. The reticle can comprise multiple alignment subfields disposed at respective positions around the pattern field. The alignment pattern can be disposed at a distance, from an adjacent boundary of the alignment subfield, that is a function of the magnitude of a proximity effect otherwise imparted to the circuit pattern by an exposure dose applied to the alignment pattern.
In a second example embodiment, the pattern field in a reticle as summarized above is circumscribed by a pattern-field boundary collectively defined by respective sides of peripheral circuit subfields of the pattern field. In such a configuration, the alignment pattern is situated a distance, from an adjacent portion of the pattern-field boundary, that is a function of the magnitude of the proximity effect otherwise imparted to the circuit pattern by an exposure dose applied to the alignment pattern.
A third representative embodiment of a reticle according to the invention comprises circuit elements to be exposed onto a wafer by a charged particle beam. The reticle also includes an alignment pattern to be exposed onto the wafer by the charged particle beam. The alignment pattern is disposed adjacent respective circuit elements but at a distance, from the adjacent circuit elements, that is a function of a magnitude of proximity effect otherwise imparted to the circuit elements by an exposure dose applied to the alignment pattern. The proximity effect otherwise imparted to the circuit elements generally is of a magnitude that would be manifest on circuit elements larger than a threshold size.
A fourth example embodiment of a reticle according to the invention comprises a pattern field and a scribe area. The pattern field is segmented into multiple pattern subfields each defining a respective portion of a pattern defined by the pattern field. Each respective portion comprises at least one respective pattern element. The scribe area surrounds the pattern field and comprises at least one alignment subfield defining an alignment-mark pattern. The alignment subfield is situated adjacent the closest pattern subfield situated in the pattern field. The distance at which the alignment-mark pattern is located from the respective elements defined in the closest pattern subfield desirably is greater than a threshold value sufficient to maintain a proximity effect of the respective elements and the alignment mark with each other below a target magnitude.
According to another aspect of the invention, charged-particle-beam (CPB) microlithography apparatus are provided. Such apparatus are used for transferring a pattern, defined by a reticle segmented into circuit subfields, and at least one alignment subfield from the reticle to a sensitive substrate. An example embodiment of such an apparatus comprises an illumination system, a projection system, and a controller. The illumination system is configured and situated to illuminate the circuit subfields and alignment subfield on the reticle with a charged particle beam. The projection system is configured and situated to deflect the charged particle beam, propagating from the alignment subfield, to a substrate. The alignment subfield, which defines an alignment mark, is situated adjacent a respective circuit subfield that defines a respective pattern element. The controller is connected to the projection system and is configured to cause the projection system to deflect the charged particle beam propagating from the alignment subfield. The magnitude of the deflection is a function of the proximity effect that would otherwise be manifest between the pattern element in the adjacent circuit subfield and the alignment mark due to an exposure dose applied to the alignment mark. The controller can be configured to cause the projection system to deflect the charged particle beam from the alignment subfield to a position, on the substrate, relative to a projected position of the adjacent circuit subfield where the proximity effect is less than a threshold value. The controller alternatively can be configured to cause the projection system to deflect the charged particle beam from the alignment subfield so as to project an image of the alignment mark onto the substrate at a position, relative to a projected position of the pattern element defined in the adjacent circuit subfield, where the proximity effect is less than a threshold value.
According to another aspect of the invention, methods are provided for manufacturing a semiconductor device. An example embodiment of such a method comprises any of various wafer-processing steps in combination with a step in which a pattern is exposed onto a resist layer using a CPB microlithography apparatus according to the invention.
According to yet another aspect of the invention, methods are provided, in conjunction with methods for performing microlithography of a circuit pattern (defined on a segmented reticle) onto a sensitive substrate using a charged particle beam, for reducing proximity effects. In such a proximity-effect-reducing method, a reticle is provided that comprises a pattern field including multiple circuit subfields in which are disposed respective circuit elements of a circuit pattern defined by the reticle. The reticle also includes at least one alignment subfield in which a respective alignment pattern is disposed. The alignment subfield is disposed outside the pattern field but adjacent a respective circuit subfield. The respective adjacent circuit subfield is projected onto the sensitive substrate. The alignment subfield is projected onto the sensitive substrate such that a projected image of the alignment pattern is located a distance from elements defined by the respective adjacent circuit subfield at which a proximity effect of the elements with the alignment pattern is maintained below a pre-determined threshold level. In this method, the circuit subfields can be projected into a pattern field on the substrate, and the alignment subfield can be projected into a scribe area that surrounds the pattern field on the substrate. The alignment subfield can be projected into the scribe area such that an edge of the alignment subfield is located a prescribed distance from a proximal edge of the adjacent circuit subfield.
According to another example method for reducing proximity effects arising from backscattering of electrons in the substrate, a corrective reticle is provided that corresponds to a patterning reticle (the patterning reticle defines the elements of the pattern). From the patterning reticle, the pattern elements are projected into a chip field as formed by the pattern elements on the substrate. A charged particle beam is irradiated through the corrective reticle onto the substrate such that the beam irradiating the substrate is incident on at least a portion of a perimeter zone located outside the chip field as projected onto the substrate. The method can further comprise the step of establishing a width of the perimeter zone based on an acceleration voltage of the charged particle beam incident on the reticle.
According to another aspect of the invention, corrective reticles are provided for reducing proximity effects in a chip field as projected onto a sensitive substrate using a charged particle beam. The corrective reticle desirably is configured to mask and transmit respective portions of the charged particle beam such that the transmitted portion of the beam irradiates at least a portion of a perimeter zone located outside the chip field as projected onto the substrate. The corrective reticle can be configured to pass a perimeter-zone-illuminating portion of the charged particle beam. Such a perimeter-zone-illuminating portion has a width, as irradiated onto the substrate, that is a function of an acceleration voltage applied to the beam irradiating the corrective reticle.
According to yet another aspect of the invention, methods are provided, in the context of methods for performing charged-particle-beam microlithography of a pattern, defined in a chip pattern on a reticle, to a sensitive substrate, for forming an alignment mark on the substrate. An example embodiment of such a method includes the step of establishing a chip-pattern area on the sensitive substrate in which an image of the chip pattern, as defined on the reticle, is exposed. An alignment mark is defined on a reticle. Using the charged particle beam, an image of the alignment mark is exposed onto the substrate. The image of the alignment mark is exposed at a location, outside the image of the chip pattern, situated at least a pre-determined threshold distance from the image of the chip pattern. The threshold distance is sufficient to maintain a magnitude of proximity effects of the image of the alignment mark with features of the chip pattern below a threshold level. For example, if the charged particle beam is an electron beam, the threshold distance (xcex4d, in xcexcm) is determined to be Avxe2x88x9235, wherein Av is an acceleration voltage (in KV) applied to the charged particle beam as used for exposure.
According to yet another aspect of the invention, methods are provided, in the context of performing charged-particle-beam microlithography of a pattern, defined in a chip pattern on a reticle, to a sensitive substrate, for reducing proximity effects arising between an alignment mark, located outside the chip pattern, and one or more elements of a pattern as exposed onto the substrate. In general, in such methods, proximity-effect corrections are performed considering the alignment mark and the chip pattern as a single unit. This allows proximity-effect correction to be performed by any of various techniques, such as by reshaping one or more of the alignment mark and an element of the chip pattern; controlling a dose of the charged particle beam as incident on the substrate; or ghosting.